RakeKiller wrote:
> I posted this at alt.comp.hardware.homebuilt and got this response...
> "Looks pretty convincing evidence that it doesnt like those two sticks at
> once for some reason."
> hopefully someone here has a bit more input...
>
> Just installed an ECS nforce3-a board. 2x512 micron pc3200 ram i get
> beeeeeep, pause, beeeeeep pause, etc.
> Took out one stick...boots fine
> switched sticks, boots fine
> both sticks in but switch slot positions, same error.
> It seems the award bios is proprietary ...
> http://www.pchell.com/hardware/beepcodes.shtml#phoenix
>
> Can anyone tell me what the issue may be that beep structure?
>
> Award BIOS Type Phoenix - AwardBIOS v6.00PG
> Award BIOS Message Nforce3-A Ver 1.0F 09/16/2005
>
> CPU Type AMD Athlon 64, 1800 MHz (9 x 200) 2800+
> CPU Alias Newcastle S754
> CPU Stepping DH-CG
> Instruction Set x86, x86-64, MMX, 3DNow!, SSE, SSE2
> Min / Max CPU Multiplier 4x / 9x
> L1 Code Cache 64 KB (Parity)
> L1 Data Cache 64 KB (ECC)
> L2 Cache 512 KB (On-Die, ECC, Full-Speed)
>
> Memory Module Properties
> Serial Number None
> Module Size 512 MB (2 ranks, 4 banks)
> Module Type Unbuffered
> Memory Type DDR SDRAM
> Memory Speed PC3200 (200 MHz)
> Module Width 64 bit
> Module Voltage SSTL 2.5
> Error Detection Method None
> Refresh Rate Reduced (7.8 us), Self-Refresh
>
> Memory Timings
> @ 200 MHz 3.0-3-3-8 (CL-RCD-RP-RAS)
> @ 166 MHz 2.5-3-3-7 (CL-RCD-RP-RAS)
> @ 133 MHz 2.0-2-2-6 (CL-RCD-RP-RAS)
>
> Memory Module Features
> Early RAS# Precharge Not Supported
> Auto-Precharge Not Supported
> Precharge All Not Supported
> Write1/Read Burst Not Supported
> Buffered Address/Control Inputs Not Supported
> Registered Address/Control Inputs Not Supported
> On-Card PLL (Clock) Not Supported
> Buffered DQMB Inputs Not Supported
> Registered DQMB Inputs Not Supported
> Differential Clock Input Supported
> Redundant Row Address Not Supported
>
> 600 watt PS
> 9800 Pro 128MB
>
Have you tested both slots separately ?
Place one stick in slot 1 and test.
Then move stick to slot 2 and test.
Just to verify that each slot works individuall.
The motherboard has less to do with it, than in other
architectures. Athlon64 has the memory controller on the processor.
The socket 754 has two address busses, but is single channel on the
data bus. Since your motherboard has two slots, ECS could wire it
so one address bus goes to slot 1 and one address bus goes to slot 2.
When means, for control and address, one slot can fail without
upsetting the other.
But the motherboard contribution is just the wires and sockets.
The memory talks to the processor directly, meaning digitally,
the motherboard plays less of a role.
The motherboard will have a regulator to power the DIMM slots. And
it is possible that the two DIMMs are too much load from a power
perspective. (Mentioned for completeness, but highly unlikely to
be the problem.)
The SPD on each DIMM, sits on a common bus. The SMBUS is a serial
bus, and each DIMM slot should be wired to the same bus. If the
motherboard was having trouble reading the SPD, it would take a
dirty pin in the socket, as with SMBUS totally dead, neither slot
would work.
So right now, I don't have a good theory as to what is
wrong. If a single stick in either slot works, then electrically
everything is in good shape. Could be a motherboard Vdimm regulator
problem, but unlikely. Could be a short to the bottom of the motherboard,
only happening when you press on it. You could remove the motherboard
from the case and test everything again, but the odds are slim that
the test results will differ.
The data bus is shared by the two slots, and the processor. But
double the loading on the data bus, is not quite the same kind of
loading as occurs on address/control. So would not be a suspect.
Again, a dirty pin in one socket, would make one socket fail. But
if both sockets test good, then that isn't it.
Is the BIOS up to date ? Maybe it is a BIOS issue ?
Can you dump the SPD for both sticks ? CPUZ has an option to
do that. The info looks like this. Basically CPUZ is getting
this from the SPD chip, via the SMBUS.
Dump Module #1
0 1 2 3 4 5 6 7 8 9 A B C D E F
00 80 08 07 0D 0A 02 40 00 04 50 65 00 82 08 00 01
10 0E 04 1C 01 02 20 00 60 70 75 75 38 28 38 28 40
20 60 60 40 40 00 00 00 00 00 37 46 20 28 50 00 00
30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8C
40 7F 98 00 00 00 00 00 00 00 4B 00 00 00 00 00 00
50 00 00 00 00 00 00 00 00 00 00 00 00 00 63 09 06
60 FF FF 04 00 00 00 00 00 00 00 00 00 00 00 00 00
70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
On older motherboards, where one address/control bus drove
all slots, you could attribute the problem to bus loading,
and select a lower clock for the RAM. But this board has
the potential to use separate addresses, and changing the
settings really shouldn't be necessary. Only if ECS was
really slimy, and only wired up one address bus, and wired
it to both slots, would you have a loading issue, and a reason
to adjust down the clock. And ECS wouldn't do a thing
like that would they ?
Paul
Award Bios beep code? 
Linear Mode
