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Old 04-02-2007, 04:39 AM
mike
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Default ddr prefetch - performance gain for sequential access but not for random?

it's my understanding that each new sdram type doubles the bandwidth of
the previous via (among other things) a larger prefetch buffer:

type prefetch(bits)
---- --------------
sdr 1
ddr 2
ddr2 4
ddr3 8

i'm trying to determine whether the following is true or not:

prefetching increases the amount of memory read adjacent to the specified
address, or to put it another way, it reads a larger block size. so
aside from the effect of locality of reference, which can yield up to the
advertised performance gain (ie: sequential read), it doesn't improve
random access at all (by random, in this context, i mean each memory
access is outside of any buffering/caching).

i'd like to find documentation that either confirms or denies the
above, but having read a fairly large number of articles on the subject
haven't been able to determine this.



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Old 04-03-2007, 10:27 AM
GT
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Default Re: ddr prefetch - performance gain for sequential access but not for random?

"mike" <mike@localhost.localdomain> wrote in message
news:pan.2007.04.02.04.39.12.533591@localhost.loca ldomain...
> it's my understanding that each new sdram type doubles the bandwidth of
> the previous via (among other things) a larger prefetch buffer:
>
> type prefetch(bits)
> ---- --------------
> sdr 1
> ddr 2
> ddr2 4
> ddr3 8


[snip]

So does that mean that DDRII 667 is 4 times faster than DDR 333 ? Or is it
just twice the speed?



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Old 04-03-2007, 09:52 PM
mike
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Default Re: ddr prefetch - performance gain for sequential access but not for random?

On Tue, 03 Apr 2007 11:27:26 +0100, GT wrote:

> "mike" <mike@localhost.localdomain> wrote in message
> news:pan.2007.04.02.04.39.12.533591@localhost.loca ldomain...
>> it's my understanding that each new sdram type doubles the bandwidth of
>> the previous via (among other things) a larger prefetch buffer:
>>
>> type prefetch(bits)
>> ---- --------------
>> sdr 1
>> ddr 2
>> ddr2 4
>> ddr3 8

>
> [snip]
>
> So does that mean that DDRII 667 is 4 times faster than DDR 333 ? Or is it
> just twice the speed?


afaik, the memory chips for both run at 166 mhz with the ddr
prefetch yielding two bits per clock (on each of 64 lines) and ddr2
yielding four bits. so it's a doubling of bandwidth, but whether the
speed is actually doubled is the question i'm asking. in the case of
purely random data accesses to a large memory area i'm thinking that the
speed isn't increased at all because the additional data supplied by ddr2
is not used (likewise with ddr compared to sdr). i'm assuming, of course,
that the extra prefetch bits are obtained by simply taking the nearest
bits to what has already been selected for a particular memory address (as
opposed to selecting bits for a completely different memory address). that
is the issue that i'm trying to determine. my background is programming,
not hardware & chip design so it's a bit of a learning curve for me to
figure this out.

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Old 04-04-2007, 01:42 PM
GT
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Posts: n/a
Default Re: ddr prefetch - performance gain for sequential access but not for random?

"mike" <mike@localhost.localdomain> wrote in message
news:pan.2007.04.03.21.52.47.685709@localhost.loca ldomain...
> On Tue, 03 Apr 2007 11:27:26 +0100, GT wrote:
>
>> "mike" <mike@localhost.localdomain> wrote in message
>> news:pan.2007.04.02.04.39.12.533591@localhost.loca ldomain...
>>> it's my understanding that each new sdram type doubles the bandwidth of
>>> the previous via (among other things) a larger prefetch buffer:
>>>
>>> type prefetch(bits)
>>> ---- --------------
>>> sdr 1
>>> ddr 2
>>> ddr2 4
>>> ddr3 8

>>
>> [snip]
>>
>> So does that mean that DDRII 667 is 4 times faster than DDR 333 ? Or is
>> it
>> just twice the speed?

>
> afaik, the memory chips for both run at 166 mhz with the ddr
> prefetch yielding two bits per clock (on each of 64 lines) and ddr2
> yielding four bits. so it's a doubling of bandwidth, but whether the
> speed is actually doubled is the question i'm asking. in the case of
> purely random data accesses to a large memory area i'm thinking that the
> speed isn't increased at all because the additional data supplied by ddr2
> is not used (likewise with ddr compared to sdr). i'm assuming, of course,
> that the extra prefetch bits are obtained by simply taking the nearest
> bits to what has already been selected for a particular memory address (as
> opposed to selecting bits for a completely different memory address). that
> is the issue that i'm trying to determine. my background is programming,
> not hardware & chip design so it's a bit of a learning curve for me to
> figure this out.


I think DDR2-667 runs at 333MHz and DDR-333 runs at 166MHz, so I would
expect DDR2-667 to be twice the speed, but I can't comment on the prefetch
thing, but if you are right, then DDR2-667 is potentially 4 times faster
than DDR-333.



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  #5 (permalink)  
Old 04-04-2007, 03:41 PM
mike
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Posts: n/a
Default Re: ddr prefetch - performance gain for sequential access but not for random?

On Wed, 04 Apr 2007 14:42:21 +0100, GT wrote:

> "mike" <mike@localhost.localdomain> wrote in message
> news:pan.2007.04.03.21.52.47.685709@localhost.loca ldomain...
>> On Tue, 03 Apr 2007 11:27:26 +0100, GT wrote:
>>
>>> "mike" <mike@localhost.localdomain> wrote in message
>>> news:pan.2007.04.02.04.39.12.533591@localhost.loca ldomain...
>>>> it's my understanding that each new sdram type doubles the bandwidth of
>>>> the previous via (among other things) a larger prefetch buffer:
>>>>
>>>> type prefetch(bits)
>>>> ---- --------------
>>>> sdr 1
>>>> ddr 2
>>>> ddr2 4
>>>> ddr3 8
>>>
>>> [snip]
>>>
>>> So does that mean that DDRII 667 is 4 times faster than DDR 333 ? Or is
>>> it
>>> just twice the speed?

>>
>> afaik, the memory chips for both run at 166 mhz with the ddr
>> prefetch yielding two bits per clock (on each of 64 lines) and ddr2
>> yielding four bits. so it's a doubling of bandwidth, but whether the
>> speed is actually doubled is the question i'm asking. in the case of
>> purely random data accesses to a large memory area i'm thinking that the
>> speed isn't increased at all because the additional data supplied by ddr2
>> is not used (likewise with ddr compared to sdr). i'm assuming, of course,
>> that the extra prefetch bits are obtained by simply taking the nearest
>> bits to what has already been selected for a particular memory address (as
>> opposed to selecting bits for a completely different memory address). that
>> is the issue that i'm trying to determine. my background is programming,
>> not hardware & chip design so it's a bit of a learning curve for me to
>> figure this out.

>
> I think DDR2-667 runs at 333MHz and DDR-333 runs at 166MHz, so I would
> expect DDR2-667 to be twice the speed, but I can't comment on the prefetch
> thing, but if you are right, then DDR2-667 is potentially 4 times faster
> than DDR-333.


i was going by what it says here:

http://en.wikipedia.org/wiki/DDR2_SDRAM

in table "Chips" it shows the "memory clock" for DDR2-667 as 166 mhz.
it also shows the bus clock at 333 mhz but i think that takes into account
the effect of using prefetch.

i believe it breaks down as in the following table where ddr yields double
the underlying memory chip speed (mhz) and ddr2 quadruples it:

mhz 2-bit prefetch 4-bit prefetch
--- --------------- ------------------
100 DDR-200(PC-1600) DDR2-400(PC2-3200)
133 DDR-266(PC-2100) DDR2-533(PC2-4200)
166 DDR-333(PC-2700) DDR2-667(PC2-5300)
200 DDR-400(PC-3200) DDR2-800(PC2-6400)


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