On Tue, 16 Aug 2005 11:16:30 +0000 (UTC), "Oenone"
>I've ordered a custom build PC with the following specification:
>MSI K8N Neo4 Platinum-SLI motherboard
>AMD Athlon 64 3500+ CPU
>1Gb CL2.0 PC3200 DDR RAM
>Radeon X800XL graphics card
>Unfortunately the company have run out of the CL2.0 memory and currently
>only have 3.0 in stock.
>Would the group recommend that I wait for the CL2.0 memory to come in or is
>the difference between the two not enough to worry about?
>The PC will be used for high-end gaming.
CL2.0 = CAS-2 = Column Address Strobe 2 clock cycles
The numbers you are refering to represent the number of clock cycles
required to access or activate the various rows and columns of the RAM
modules or memory banks. But there is more to it than that and
requires you to understand just how memory works before you can decide
if super fast settings will appreciably affect the performance of your
particular setup and programs. The ability to quickly transfer large
amounts of data may not be necessary for your end use. If you have a
quality, and fast processor you will only need fast RAM modules if
your computer will be computing a lot or encoding video. For any other
application, including games, slower RAM is fine.
" Think of a clock cycle as one tick of the second hand (but generally
at a much higher speed). Computer clocks run voltage through a tiny
crystal that oscillates at a predictable speed to give a meaningful
timing method to the computer. One clock cycle doesn't necessarily
mean that the processor does one operation. Today's high-end
processors often complete more than one operation per clock cycle, and
other times, in the worst cases, it will take several clock cycles to
complete one operation."
Tom's Hardware has a good primer for understanding these numbers http://www.tomshardware.com/motherboard/20040119/
Here is a quote:
"Information is stored by first separating the memory area into rows
and columns. The capacity of the individual chips determines the
number of rows and columns per module. When several arrays are
combined, they create memory banks.
The chips are actually accessed by means of control signals such as
row address strobe (RAS), column address strobe (CAS), write enable
(WE), chip select (CS) and several additional commands (DQ).
In today's computers, a command rate is defined in BIOS - generally
1-2 cycles. This describes the amount of time it takes for the RAS to
be executed after the memory chip has been selected.
The memory controller selects the active row. But before the row will
actually become active so that the columns can be accessed, the
controller has to wait for 2-3 cycles - tRCD (RAS-to-CAS delay). Then
it sends the actual read command, which is also followed by a delay -
the CAS latency. For DDR RAM, CAS latency is 2, 2.5 or 3 cycles. Once
this time has lapsed, the data will be sent to the DQ pins. After the
data has been retrieved, the controller has to deactivate the row
again, which is done within tRP (RAS precharge time).
There is one more technical restriction - tRAS (active-to-precharge
delay). This is the fewest number of cycles that a row has to be
active before it can be deactivated again. 5-8 cycles are about
average for tRAS."
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