what happenswhen motherboard specifiction has specified that memory
frequency supported are: 533mhz and 667mhz but along the one module of
1GB 667mhy we install 1GB 800mhz modulewhich works and is
"compatible" , technically speaking what happens ?
i know it has to dowith the oscilator oscilating of frequencies but i
can^t find the reasonable technically written text about what is being
done with putting twomemory modules of a different frequencies side-by-
side...
am looking for a more complicated explanation than "it isworking"
explanation.
so are the chips somehow streched or what...
iknow some modules have been made in the manner to be compatible with
the lower frequencies thentheir upmost is 800mhz -> 667mhz so these
are clearer for a user tocomprehend as they were adjusted for
compatibility with the lower frequency at the factory which has
produced them.
the questionis about the modules whichdo not have factory made (or
not specified) capability to adjust to lower freqeuncy also, but they
do work on that lower freqency. Ihave a thiny black hore, what is
lowering the frequency if it is not being lowered automaticly, when
the possible setting is being recognized by an automatism, and is it
harmfulll for the chip, if somekind of forced streching of module-
chips is happening !????
comitter wrote:
> what happenswhen motherboard specifiction has specified that memory
> frequency supported are: 533mhz and 667mhz but along the one module of
> 1GB 667mhy we install 1GB 800mhz modulewhich works and is
> "compatible" , technically speaking what happens ?
>
> i know it has to dowith the oscilator oscilating of frequencies but i
> can^t find the reasonable technically written text about what is being
> done with putting twomemory modules of a different frequencies side-by-
> side...
>
> am looking for a more complicated explanation than "it isworking"
> explanation.
>
> so are the chips somehow streched or what...
>
> iknow some modules have been made in the manner to be compatible with
> the lower frequencies thentheir upmost is 800mhz -> 667mhz so these
> are clearer for a user tocomprehend as they were adjusted for
> compatibility with the lower frequency at the factory which has
> produced them.
>
> the questionis about the modules whichdo not have factory made (or
> not specified) capability to adjust to lower freqeuncy also, but they
> do work on that lower freqency. Ihave a thiny black hore, what is
> lowering the frequency if it is not being lowered automaticly, when
> the possible setting is being recognized by an automatism, and is it
> harmfulll for the chip, if somekind of forced streching of module-
> chips is happening !????
>
For simplicity of design, the memory controller runs both memory
channels at the same speed and timing.
The memory chips can tolerate a large range of clock frequencies.
They're not fixed at one speed. In some cases, they can handle a
range of more than 2x in frequency.
Synchronous DRAM, is a control overlay on top of asynchronous behavior.
For example, say an activity inside the memory chip takes 118ns to
complete. Further, assume the period of the clock signal feeding
the memory chip is 20 nanoseconds. The circuits inside the chip,
basically measure time in units of clock cycles. The nearest
cycle to completion in this example, is 6 cycles. So the memory
chip control logic, would look for a result at the 120ns mark, by
using 6 periods of 20ns for measurement purposes. This is slightly
longer than the 118ns actual time for the activity to be complete,
by a couple nanoseconds.
As a result, when you change the clock frequency (and corresponding
time period), the number of cycles to wait, has to change as well.
In my example, say I change the clock period from 20 ns to 15 ns.
That is an increase in the frequency. Now, I need to do the math
again, do 118/15= 7.86 and round up to the nearest cycle which is 8.
Then, in the BIOS, I would change a timing from 6 to 8, after
making the change in frequency (then save the settings). That
maintains the necessary period (118ns or greater) that is needed
for the memory chip to work inside. That is a "scaling" of timing
parameters, as a function of the clock choice.
When you mix the two DIMMs with different speed and timing, the
slowest settings common to both modules are used. That ensures
both modules have sufficient time to complete their activities.
Say one DIMM needs 118ns to complete the activity, and the other
one needs 126ns to complete the activity. Say the clock period
is set at 20ns. The timing will be set to "7" or 140ns, to
accomodate the slower 126ns module. The fast module, the 118ns
module, is finished well ahead of time, and gets to "snooze" while
waiting for the other one to catch up :-) The slower module has
dominated the timing setting, and forced the usage of "7".
i just have doubt that something goes crappy with the modules when
they are put together and they are of differented Stated frequencies.
Conclusion to that would be, as i saw some number of motherboards on
which users have had right that combination-the mix of modules with
different frequencies and different brand-products. That motherboards
have had somekind of problems.
I can't confirm that, so i'm exploring, trying to find out what
actually is happening within the modules with the data and what is
actually frequency which etc...can't find the literature for it, and
can't afford to hire an engineer for explanations ;)
I did heard of Numa and such expressions, but i would need to know
deep deep stuff about mechanism of data passing in memory and how it
is actually working, and what are the differences in various modules-
brands which could theoretically or proven in using that combination,
what harm could be done...to motherboard, modules, other components.
And yes it is complicated then that, i have been reading all kind of
stuff about the way it is working and it is not so easy to comprehend,
just it is odd and detracting materia to go into deep... it goes down
to architecture of mbos and so on...
i would need to understand where is a problem, if not just a
bottleneck which is possible to resolve with hardware components
change...
so if there is a problem, i would have to know how to locate it, if it
is a chipset which is not handling the data beacuse of some
incompatibility in correlation with the CPU, then what part to change,
the cpu or the ram memory, and of course one tragic solution for when
to change a memory modules, as the products do vary and are different,
so i can't find a real logic in this part, people really mostly just
buy products and they install them, never concerning about what and
how it works with their motherboard/chipset, i just want to know what
to propose to them and why is that better then some other component in
the wide.world offer...
Ok, it is also a bahaving of a user, if it's a gamer he or she will
take some mean.dangerous stuff as that has it's function for gaming,
in gaming correlating with the chipset and the CPU. Then you have sort
of people which have to have just open-free system for every-day
activities like ton of e-mails, various multimedia programs, apps,
that sort of stuff, then you have more and less ocupied business users
which every of them has it's own way and own programs and it's own
operating systems.
Then you have operation systems which don't behave the same on same
hardware basis, anybody follows me in this ?
bymyfault wrote:
>
> i would need to understand where is a problem, if not just a
> bottleneck which is possible to resolve with hardware components
> change...
>
> so if there is a problem, i would have to know how to locate it, if it
> is a chipset which is not handling the data beacuse of some
> incompatibility in correlation with the CPU, then what part to change,
> the cpu or the ram memory, and of course one tragic solution for when
> to change a memory modules, as the products do vary and are different,
> so i can't find a real logic in this part, people really mostly just
> buy products and they install them, never concerning about what and
> how it works with their motherboard/chipset, i just want to know what
> to propose to them and why is that better then some other component in
> the wide.world offer...
>
> Ok, it is also a bahaving of a user, if it's a gamer he or she will
> take some mean.dangerous stuff as that has it's function for gaming,
> in gaming correlating with the chipset and the CPU. Then you have sort
> of people which have to have just open-free system for every-day
> activities like ton of e-mails, various multimedia programs, apps,
> that sort of stuff, then you have more and less ocupied business users
> which every of them has it's own way and own programs and it's own
> operating systems.
>
> Then you have operation systems which don't behave the same on same
> hardware basis, anybody follows me in this ?
>
With regard to Nforce2, the issue there was the Northbridge is
not really capable of running at DDR400 speeds. And the part that
I could not understand, is how a CAS2 module at DDR400 speed would
work fine, while a CAS3 module would not. With the CAS3, perhaps I could
achieve error free operation at around DDR370 or so. There really should
not be a dependency on the CAS value like that (synchronous operation means
meeting timing at the clock edge, and the behavior I was seeing suggested
a clock edge wasn't being used for all operations).
The chips themselves, have "stub capacitance", which affects the
reflections they create on the memory bus. A different brand of chips,
probably does not match the capacitance of a competitor. JEDEC proposed
adding chip caps to balance this kind of thing out, but that is just
silly. Nobody is going to do that.
As far as I know, the layout makes such differences unimportant anyway.
The chips are laid out with T-branch topology. When I simulated layout
structures like this at work, if you keep things relatively symmetric, the
reflections tend to cancel out. Although I doubt my results were
as clean looking, as the eye diagrams here. Minor differences in the chips
don't matter too much because of the tendency to cancel.
For other situations and motherboards, I don't think I can present any
convincing theories, as to why certain combinations would not work. The
thing is, the older memory bus standards are really horrible, in terms of
how the signals look. So it would not take too much degradation when moving
modules around, to cause a small number of errors to occur. Sometimes, if
you have three slots, you'll find moving the DIMMs to different slots, makes
a minor difference.
And there are some modules, which are designed wrong. The modules which use
x4 width chips, don't "agree" with some of the Intel chipsets. Mushkin tested
modules like that years ago (the web site information has been removed, and
no archival copies are available). Basically, only one chipset (VIA?) could
drive three modules using x4 chips. Some motherboards couldn't even drive one
of those modules.
But for the more conventional modules, with x8 or x16 width chips, I don't
know if I could predict there will be trouble or not, just by looking at them.
Sometimes, there are known issues with certain releases of chips (like Micron D9
perhaps), and there are some enthusiasts who buy and test enough modules, to
tell you which chip brands to avoid. I don't do enough testing, or read enough
reports, to offer advice of that nature.
You really should be able to mix them.
And to detect problems with mixing them, you would need a very fancy
digital sampling scope and some means to connect and take pictures
of the electrical signals.
> With regard to Nforce2, the issue there was the Northbridge is
> not really capable of running at DDR400 speeds. And the part that
> I could not understand, is how a CAS2 module at DDR400 speed would
> work fine, while a CAS3 module would not. With the CAS3, perhaps I could
> achieve error free operation at around DDR370 or so.
Yes, i think so too, i really don't know that much about manufacture
processes and architecture
so i could say some smart solution. I really bypass all the nonsenses
by trial and error version of
"how to solve the problems", it's about knowing the basis and using
the playground with what could be better for a User to put into their
slots.
I have read somewhere that CAS3 could also make some problems
generating them if the AMD CPU XP 3000 or 3200+ is used with the
PC3700 memory bandwith.
Some kind of nonfunctional data translation ....It's the cpu has to be
oveclocked to work fine with this kind of memory bandwidth...
There really should
> not be a dependency on the CAS value like that (synchronous operation means
> meeting timing at the clock edge, and the behavior I was seeing suggested
> a clock edge wasn't being used for all operations).
>
> The chips themselves, have "stub capacitance", which affects the
> reflections they create on the memory bus. A different brand of chips,
> probably does not match the capacitance of a competitor. JEDEC proposed
> adding chip caps to balance this kind of thing out, but that is just
> silly. Nobody is going to do that.
>
> As far as I know, the layout makes such differences unimportant anyway.
> The chips are laid out with T-branch topology. When I simulated layout
> structures like this at work, if you keep things relatively symmetric, the
> reflections tend to cancel out. Although I doubt my results were
> as clean looking, as the eye diagrams here. Minor differences in the chips
> don't matter too much because of the tendency to cancel.
>
> http://www.bit-tech.net/hardware/mem...secrets_of_pc_...
>
I'm still loosing my bad eye on the frequencies ask-to-know
question....What really is a frequency,
and why the faster frequencies means more errors,(ok, that part i
could somehow comprehend....),
it's like a bicycle, when you use it at faster rate the chain makes
more rounds and it wastes more faster then usually,
but it get's to questions, about what is usually, and why would i
drove a bike all-the-time at the highest rate...
can't manage the superfast frequencies Q. with the high latencies as
the general rule is the lower the latencies the wider(better) the
bandwith...
> For other situations and motherboards, I don't think I can present any
> convincing theories, as to why certain combinations would not work. The
> thing is, the older memory bus standards are really horrible, in terms of
> how the signals look. So it would not take too much degradation when moving
> modules around, to cause a small number of errors to occur. Sometimes, if
> you have three slots, you'll find moving the DIMMs to different slots, makes
> a minor difference.
>
> And there are some modules, which are designed wrong. The modules which use
> x4 width chips, don't "agree" with some of the Intel chipsets. Mushkin tested
> modules like that years ago (the web site information has been removed, and
> no archival copies are available). Basically, only one chipset (VIA?) could
> drive three modules using x4 chips. Some motherboards couldn't even drive one
> of those modules.
>
> But for the more conventional modules, with x8 or x16 width chips, I don't
> know if I could predict there will be trouble or not, just by looking at them.
> Sometimes, there are known issues with certain releases of chips (like Micron D9
> perhaps), and there are some enthusiasts who buy and test enough modules, to
> tell you which chip brands to avoid. I don't do enough testing, or read enough
> reports, to offer advice of that nature.
>
> You really should be able to mix them.
>
> And to detect problems with mixing them, you would need a very fancy
> digital sampling scope and some means to connect and take pictures
> of the electrical signals.
>
That's a complicated nature of the job. That person would have to know
more then i do about the memory stuff(and that's very easy!),
and he must know a lot about electronics and physics so to know how
things are working etc....then to measure such sophisticated stuff.
Definately he would need to have a knowledge about reading out that
signals....to me it just sounds futuristic; "a digital sampling
scope".
a ram memory question - what happens when 
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