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  #1 (permalink)  
Old 05-15-2008, 11:33 AM
Peter Olcott
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Default Why does 800 mhz RAM require a 1600 mhz FSB?

http://www.dell.com/content/products...=04&l=en&s=bsd

Speed 667MHz and 800MHz fully buffered ECC DIMMs
Note: 800MHz memory requires 1600MHz FSB processor

Aren't the front side bus and memory speed supposed to
be matched?



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  #2 (permalink)  
Old 05-15-2008, 01:00 PM
Dave
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Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?


"Peter Olcott" <NoSpam@SeeScreen.com> wrote in message
news:IcVWj.20465$MQ1.1492@newsfe11.phx...
>
> http://www.dell.com/content/products...=04&l=en&s=bsd
>
> Speed 667MHz and 800MHz fully buffered ECC DIMMs
> Note: 800MHz memory requires 1600MHz FSB processor
>
> Aren't the front side bus and memory speed supposed to be matched?
>
>


That is a persistent and totally untrue rumor which just refuses to die.
Computers haven't had a single clock speed in so long that I can't even
remember when that stopped being the case. But it was a
loooooooonnnnnnnnngggggggggg time ago (decades?). In general, the
motherboard chipset determines what RAM is supported, and the RAM has NO
RELATION at all to the installed CPU.

However, certain CPUs have memory controllers built into them. I don't know
about the Xeon like in the link you listed. It's possible that the Xeon has
a memory controller. That might explain why it says 800MHz memory requires
1600MHz FSB processor. That would make sense, as it would simply divide the
clock speed by two to run the RAM.

But obviously, even if you have a 1600MHz FSB processor with 800MHz RAM, the
CPU and RAM are not matched. So even in THIS case, you don't need to match
RAM to FSB. -Dave


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  #3 (permalink)  
Old 05-15-2008, 01:14 PM
kony
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Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?

On Thu, 15 May 2008 06:33:00 -0500, "Peter Olcott"
<NoSpam@SeeScreen.com> wrote:

> http://www.dell.com/content/products...=04&l=en&s=bsd
>
> Speed 667MHz and 800MHz fully buffered ECC DIMMs
> Note: 800MHz memory requires 1600MHz FSB processor
>
> Aren't the front side bus and memory speed supposed to
>be matched?
>


Often they are matched, but often modern chipsets can run
asynchronous clock rates for the two and then use a divider
to determine the ratio like 1:1, 1:1.2, 1:1.25, 1:1.5
(FSB:Memory)


However, in this case they are "matched", they just used the
wrong terms in explaining it.

800MHz in DDR2 terms really means 400MHz bus clock x 2 (2
as-in DOUBLE data rate memory) = 800

1600MHz in FSB terms really means 400MHz bus clock x 4 (4
as-in quad pumped data rate) = 1600

So you do actually have synchronous clock rates in this
case, 400:400 or 1:1.

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  #4 (permalink)  
Old 05-15-2008, 02:03 PM
Gumby
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Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?

kony <spam@spam.com> wrote in
news:bjco241cv2qeearbaemhbs0dmdo8ekb40j@4ax.com:

> Often they are matched, but often modern chipsets can run
> asynchronous clock rates for the two and then use a divider
> to determine the ratio like 1:1, 1:1.2, 1:1.25, 1:1.5
> (FSB:Memory)
>
>
> However, in this case they are "matched", they just used the
> wrong terms in explaining it.
>
> 800MHz in DDR2 terms really means 400MHz bus clock x 2 (2
> as-in DOUBLE data rate memory) = 800
>
> 1600MHz in FSB terms really means 400MHz bus clock x 4 (4
> as-in quad pumped data rate) = 1600
>
> So you do actually have synchronous clock rates in this
> case, 400:400 or 1:1.
>


Yea, this is how it works but you can set any ram to any speed in the mb
bios so there is no requirement that you have to have 800mhz ram. You just
have to make sure you buy ram that can do 800mhz or better if you want the
cpu and ram to run synchronously.

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  #5 (permalink)  
Old 05-15-2008, 04:10 PM
Paul
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Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?

Peter Olcott wrote:
> http://www.dell.com/content/products...=04&l=en&s=bsd
>
> Speed 667MHz and 800MHz fully buffered ECC DIMMs
> Note: 800MHz memory requires 1600MHz FSB processor
>
> Aren't the front side bus and memory speed supposed to
> be matched?
>
>


That motherboard uses FBDIMMs, a technology that adds an extra
layer of buffering, between the memory chips and the Northbridge.

The motherboard uses the 5400 chipset. Page 202 shows how the
Northbridge is dictating a relationship between the FSB and
the memory. Notice that dividers other than 1:1 are available,
so in fact it doesn't have to stay at 1:1. The information
in the table was particularly poorly written (the table existed
in another document, and a couple lines were added, presumably
by a different tech writer).

http://download.intel.com/design/chi...hts/318610.pdf (page 202)

Page 8 here, shows a single FBDIMM channel. The 5400 has four
of these.

http://download.micron.com/pdf/prese...icron_2004.pdf

The datasheet here for an FBDIMM, shows an ordinary array of
memory chips like on desktop DIMMs (see page 5 - the diagram is
not actually for the product in question, but I'll ignore that
- it still illustrates the concepts). So at least the bandwidth
of the memory chips themselves will be similar (64 bit wide rank
times the DDR2-xxx rate in terms of actual user data).

http://www.corsair.com/_datasheets/CM72FB1024.pdf

The thing is, by the time the data has been moved from the memory side of
the 5400, to the FSB side, the relationship between the bandwidths
has kinda been lost. On the one hand, two processors at
FSB1600 * 8 = 12.8GB/sec, matches four (DDR2-800 * 8 or 6400GB/sec)
DIMMs, but the bus between the 5400 and AMB has an impact on the
transfer of data. Memory busses are seldom 100% efficient (even if the
AMB was missing, it might be 65%), which means you don't get nearly
the bandwidth expected. That is why, on desktop systems, there is
still some performance improvement as the memory clock is increased
past the "balance" point clock-wise. So more theoretical memory
bandwidth should be available than is present on the FSB, to
get closer to a true balance.

10pair
Proc --- FSB --- 5400 <---- AMB <---> Memory
1 of 2 1 of 4 ----> Chips
shown channels 14pair DDR2-800
Half duplex

|<--------- FBDIMM ---------->|

I think this fits in the catagory of "don't worry about it" :-)

To read an article about another product using 5400 Northbridge,
try this one. I would have preferred they use four FBDIMMs
to test, or compare two FBDIMMs to four FBDIMMs, to see if
there is a real difference. With two FBDIMMs installed, they
measured 7147MB/sec. (The chipset has two branches, and two
channels per branch. The two DIMMs would be installed on the
same branch, one per channel, for a sort of "dual channel"
operation.)

http://www.hothardware.com/articles/...75_x_2/?page=2
http://www.hothardware.com/articleim...sandra_mem.jpg

Tomshardware used four DIMMs. And what is interesting, is there
is little difference in the Sandra bandwidth number, both when
comparing to two sticks from the Hothardware article, and when
the CPU core clock rate changes. Of course, comparing benchmarks
between sites is a "bad thing", because they might not have tested
exactly the same way.

http://www.tomshardware.com/reviews/...3,1770-17.html

Paul

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  #6 (permalink)  
Old 05-15-2008, 10:47 PM
DaveW
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Posts: n/a
Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?

800 MHz RAM does NOT require a 1600 MHz FSB. Where did you hear that?

--
--DaveW


"Peter Olcott" <NoSpam@SeeScreen.com> wrote in message
news:IcVWj.20465$MQ1.1492@newsfe11.phx...
>
> http://www.dell.com/content/products...=04&l=en&s=bsd
>
> Speed 667MHz and 800MHz fully buffered ECC DIMMs
> Note: 800MHz memory requires 1600MHz FSB processor
>
> Aren't the front side bus and memory speed supposed to be matched?
>
>




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  #7 (permalink)  
Old 05-16-2008, 05:19 AM
kony
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Posts: n/a
Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?

On Thu, 15 May 2008 14:03:58 GMT, Gumby <gumby@is.cool>
wrote:

>kony <spam@spam.com> wrote in
>news:bjco241cv2qeearbaemhbs0dmdo8ekb40j@4ax.com :
>
>> Often they are matched, but often modern chipsets can run
>> asynchronous clock rates for the two and then use a divider
>> to determine the ratio like 1:1, 1:1.2, 1:1.25, 1:1.5
>> (FSB:Memory)
>>
>>
>> However, in this case they are "matched", they just used the
>> wrong terms in explaining it.
>>
>> 800MHz in DDR2 terms really means 400MHz bus clock x 2 (2
>> as-in DOUBLE data rate memory) = 800
>>
>> 1600MHz in FSB terms really means 400MHz bus clock x 4 (4
>> as-in quad pumped data rate) = 1600
>>
>> So you do actually have synchronous clock rates in this
>> case, 400:400 or 1:1.
>>

>
>Yea, this is how it works but you can set any ram to any speed in the mb
>bios so there is no requirement that you have to have 800mhz ram.


On many systems you can, but on that specific OEM
workstation? I would not assume it, and one of the reasons
for it's higher cost is it support more memory which may
reduce the flexibility in choosing different combinations of
speeds and timings (if again, they let you choose at all
instead of it all being hidden and unsettable "auto"
configured).

>You just
>have to make sure you buy ram that can do 800mhz or better if you want the
>cpu and ram to run synchronously.


IMO, anyone should buy -800 memory or better anyway, the
cost different is minor and if they can set speed and/or
timings they may have the potential for a faster system as a
result.


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  #8 (permalink)  
Old 05-16-2008, 10:20 PM
Peter Olcott
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Posts: n/a
Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?


"DaveW" <radiation@nuclear.org> wrote in message
news:U7CdnT6f6Z-gIbHVnZ2dnUVZ_sKqnZ2d@comcast.com...
> 800 MHz RAM does NOT require a 1600 MHz FSB. Where did
> you hear that?
>
> --
> --DaveW
>
>
> "Peter Olcott" <NoSpam@SeeScreen.com> wrote in message
> news:IcVWj.20465$MQ1.1492@newsfe11.phx...
>>
>> http://www.dell.com/content/products...=04&l=en&s=bsd
>>
>> Speed 667MHz and 800MHz fully buffered ECC DIMMs
>> Note: 800MHz memory requires 1600MHz FSB processor
>>
>> Aren't the front side bus and memory speed supposed
>> to be matched?
>>
>>

>
>


It is on the second tab of the link above, it is also
directly quoted immediately above:
>>>Note: 800MHz memory requires 1600MHz FSB processor<<<

The Intel website seems to say the same thing as a
requirement of their motherboards.



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  #9 (permalink)  
Old 05-17-2008, 09:41 PM
jameshanley39@yahoo.co.uk
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Posts: n/a
Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?

On 15 May, 14:14, kony <s...@spam.com> wrote:
<snip>
> 800MHz in DDR2 terms really means 400MHz bus clock x 2 (2
> as-in DOUBLE data rate memory) = 800
>


I knew how it worked for DDR.. Not for DDR2. So, just asking regarding
this DDR2

isn't 800 in DDR2 terms, 200MHz*4 ?

i.e. 200Mhz bus

<snip>


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  #10 (permalink)  
Old 05-18-2008, 02:24 AM
kony
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Posts: n/a
Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?

On Sat, 17 May 2008 14:41:50 -0700 (PDT),
"jameshanley39@yahoo.co.uk" <jameshanley39@yahoo.co.uk>
wrote:

>On 15 May, 14:14, kony <s...@spam.com> wrote:
><snip>
>> 800MHz in DDR2 terms really means 400MHz bus clock x 2 (2
>> as-in DOUBLE data rate memory) = 800
>>

>
>I knew how it worked for DDR.. Not for DDR2. So, just asking regarding
>this DDR2
>
>isn't 800 in DDR2 terms, 200MHz*4 ?
>
>i.e. 200Mhz bus
>
><snip>


Depends on where the clock rate comes from, AFAIK.
On DDR2-800 the memory clock is 200MHz, the bus clock
400MHz. This contrasts DDR1 where the bus clock is the same
as the memory clock frequency.

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  #11 (permalink)  
Old 05-20-2008, 03:53 AM
jameshanley39@yahoo.co.uk
Guest
 
Posts: n/a
Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?

On 18 May, 03:24, kony <s...@spam.com> wrote:
> On Sat, 17 May 2008 14:41:50 -0700 (PDT),
> "jameshanle...@yahoo.co.uk" <jameshanle...@yahoo.co.uk>
> wrote:
>
> >On 15 May, 14:14, kony <s...@spam.com> wrote:
> ><snip>
> >> 800MHz in DDR2 terms really means 400MHz bus clock x 2 (2
> >> as-in DOUBLE data rate memory) = 800

>
> >I knew how it worked for DDR.. Not for DDR2. So, just asking regarding
> >this DDR2

>
> >isn't 800 in DDR2 terms, *200MHz*4 ?

>
> >i.e. 200Mhz bus

>
> ><snip>

>
> Depends on where the clock rate comes from, AFAIK.
> On DDR2-800 the memory clock is 200MHz, the bus clock
> 400MHz. *This contrasts DDR1 where the bus clock is the same
> as the memory clock frequency.


I got it now.. Had alot of misconceptions..
articles referring to a data bus, mean memory bus.
(and IO bus means actual speed of memory bus. As oppose to effective
speed.)

so with intel p4 , AMD Athlon XP. And the core 2 duo..
They have FSB and Memory Bus.
FSB is irrelevant.

And the internal memory/data bus. Runs slow, like
DDR2-800, it runs as 200MHz
But it runs at a width to match the 800Mhz effective data bus speed.
So 4 times the width of the external data bus.

The data bus itself, whether DDR, DDR2 or DDR3 is always only dual
data rate. So DDR2-800 , data bus actual speed is 400Mhz.

And the point that when they say IO Bus . It is a funny way of saying
Actual speed of data bus (as oppose to effective speed) this is clear
from digit-life article, and verified by wikipedia article.

useful links
http://www.digit-life.com/articles2/...mma-page1.html
http://en.wikipedia.org/wiki/DDR2_SDRAM
may be some things in arstechnica articles or forum, maybe.

tx


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  #12 (permalink)  
Old 05-20-2008, 04:09 AM
jameshanley39@yahoo.co.uk
Guest
 
Posts: n/a
Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?

On 15 May, 12:33, "Peter Olcott" <NoS...@SeeScreen.com> wrote:
> *http://www.dell.com/content/products...x/precn_t7400?....
>
> * * * Speed *667MHz and 800MHz fully buffered ECC DIMMs
> * * * Note: 800MHz memory requires 1600MHz FSB processor
>
> * * * Aren't the front side bus and memory speed supposed to
> be matched?


I will have to look into this a bit, but
AMD Athlon XP, CPU dual pumps the FSB.
P4, it quad pumps it.
Don't know about core 2 duo.

Meaning, the FSB has an actual speed, and an effective speed.

1600Mhz is so high, it's blatantly an effective speed.

in an estimate.. I would guess that 1600MHz is the quad pumped speed,
and the actual speed of FSB is thus 400Mhz.
Which is the exact same speed as your Memory Bus. whose actual speed
is 400Mhz, and effective speed is 800.

I think quad pumped means sending/receiving 4 bits were data line of
the bus. In each clock cycle.

there's some kind of quartz clock thing in the computer.. which makes
signals HIGH LOW HIGH LOW with time. So if you know GCSE physics, you
get a wave

--------- ---------
!_______!- !_________
a b c
and you can measure a cycle. In physics. it is peak to peak. trough to
trough. or an in between thingy. a-b b-c or a-c.

And a bus is like many lines. I guess 1 bit per line normally.

Dual pumping sends 2 bits per line. Quad pumping sends 4 bits per
line. I think

So the idea is that if a bus operates at say 400MHz, quad pumped.
Then it is equivalent to a bus operating at 1600Mhz without being quad
pumped.

Here is just me thinking.. and it's a new thought. and I am no
engineer. This is probably completely wrong, but
From what I can see.. if 2 buses are communicating..
Say they are same speed, same width.. both same level of pump! so
just regular 1 bit per data line.
one bus could double any one of those factors. And the other bus could
double any one of them to match it. They all seem to be somewhat
equivalent.

Which is why btw, i think the internal memory clock is not pumped..it
uses the width factor. to match the effective speed of the data bus.
..
some of what i have said is probably very wrong.. I hope not too much!



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  #13 (permalink)  
Old 05-20-2008, 07:56 AM
Paul
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Posts: n/a
Default Re: Why does 800 mhz RAM require a 1600 mhz FSB?

jameshanley39@yahoo.co.uk wrote:
> On 15 May, 12:33, "Peter Olcott" <NoS...@SeeScreen.com> wrote:
>> http://www.dell.com/content/products...x/precn_t7400?...
>>
>> Speed 667MHz and 800MHz fully buffered ECC DIMMs
>> Note: 800MHz memory requires 1600MHz FSB processor
>>
>> Aren't the front side bus and memory speed supposed to
>> be matched?

>
> I will have to look into this a bit, but
> AMD Athlon XP, CPU dual pumps the FSB.
> P4, it quad pumps it.
> Don't know about core 2 duo.
>
> Meaning, the FSB has an actual speed, and an effective speed.
>
> 1600Mhz is so high, it's blatantly an effective speed.
>
> in an estimate.. I would guess that 1600MHz is the quad pumped speed,
> and the actual speed of FSB is thus 400Mhz.
> Which is the exact same speed as your Memory Bus. whose actual speed
> is 400Mhz, and effective speed is 800.
>
> I think quad pumped means sending/receiving 4 bits were data line of
> the bus. In each clock cycle.
>
> there's some kind of quartz clock thing in the computer.. which makes
> signals HIGH LOW HIGH LOW with time. So if you know GCSE physics, you
> get a wave
>
> --------- ---------
> !_______!- !_________
> a b c
> and you can measure a cycle. In physics. it is peak to peak. trough to
> trough. or an in between thingy. a-b b-c or a-c.
>
> And a bus is like many lines. I guess 1 bit per line normally.
>
> Dual pumping sends 2 bits per line. Quad pumping sends 4 bits per
> line. I think
>
> So the idea is that if a bus operates at say 400MHz, quad pumped.
> Then it is equivalent to a bus operating at 1600Mhz without being quad
> pumped.
>
> Here is just me thinking.. and it's a new thought. and I am no
> engineer. This is probably completely wrong, but
> From what I can see.. if 2 buses are communicating..
> Say they are same speed, same width.. both same level of pump! so
> just regular 1 bit per data line.
> one bus could double any one of those factors. And the other bus could
> double any one of them to match it. They all seem to be somewhat
> equivalent.
>
> Which is why btw, i think the internal memory clock is not pumped..it
> uses the width factor. to match the effective speed of the data bus.
> ..
> some of what i have said is probably very wrong.. I hope not too much!
>
>


This is quad pumped. The data bus is sampled four times per clock cycle.
I show a slight phase shift in the diagram, because in the real world, it
helps to have setup and hold time with respect to the clock edge.

|<------ 2.5 nanoseconds ------>|

+---------------+ +----
| | |
Clock signal 400MHz ----------------+ +---------------+
______ ______ ______ ______
Data bus is 1600MHz \/ \/ \/ \/ \/
/\______/\______/\______/\______/\
^ ^ ^ ^
| | | |
Sample Sample Sample Sample

The processor data bus has been 64 bits wide for some time, on Intel processors.
That is 8 bytes. At a transfer rate of 1600MHz of data, the theoretical maximum
transfer rate is 1600 * 8 = 12.8GB/sec

DDR2 DRAM has a similar drawing, except for the fact that two pieces of data are
transferred per clock cycle. (Note - I didn't put numbers on this drawing, on
purpose.) The clock here, is whatever clock is used to orchestrate bus transfers.
It may be related to the FSB clock, by a ratio of simple integers. I treat the
memory as a black box, so I cannot see the details.

|<------ ??? nanoseconds ------>|

+---------------+ +----
| | |
Clock signal X MHz ----------------+ +---------------+
______________ ______________
Data bus is 2X MHz \/ \/ \/
/\______________/\______________/\
^ ^
| |
Sample Sample

If you had a DDR2-800 memory, and the sticks are 64 bits wide on the interface
(8 bytes wide), the theoretical maximum transfer rate is 800*8 = 6400MB/sec,
which is why it would be called PC2-6400 memory. On a motherboard chipset
supporting some kind of dual channel concept, both channels deliver 6400MB/sec,
for a possible total of 12800MB/sec. So now my memory subsystem appears to
exactly matches the processor FSB transfer rate.

Now, why doesn't this matter. Well, if you look at a timing diagram for
the bus, no bus is occupied 100% of the time. With DRAM memory, you have to set
up row address and column address, before something can happen. There is a
limit as to how much the operations can be overlapped. So the data bus shown
above, will be idle part of the time.

To see an idling, inefficient memory bus, try PDF page 43. DQ is the
memory data bus. I'm much prefer a longer trace, using real world data,
as that would make it easier to explain why the memory is not 100%
efficient. The kinds of diagrams in a datasheet like this, don't show
how much overlap can be achieved between transactions.

http://download.micron.com/pdf/datas.../512MbDDR2.pdf

So the transfers are all "actual", but the bus may not be occupied on
every cycle. Bus qualification (saying whether there is data present
on the bus, on a given cycle), can be implicit or explicit. Explicit
would be a qualifier signal that says "yup, the data bus is good on
this cycle". (On the Intel FSB, these are called strobes.)

Since the memory bus may not be running 100% of the time, it helps
if we crank the memory bus further than the balance point. That helps
compensate for the dead cycles.

Systems can have other limitations, like the BIU may be limited
in how often it is ready to send stuff across the FSB. The sum
total of these effects, only become apparent when you benchmark,
as that is the easiest way to take all of this stuff into account.

The original posters question, was about a chipset using FBDIMMs.
These have an extra level of bus structure. The chipset datasheet,
without elaboration, only offers one ratio at FSB1600, making the
chipset less flexible than your average desktop. This may be a
performance optimization by Intel, to reduce latency in the
Northbridge.

Paul

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